The present invention relates generally to semiconductor fabrication and more specifically to semiconductor MOSFET device fabrication.
As MOSFET (metal oxide semiconductor field effect transistor) gate length decreases, the unit power gain frequency (fMAX) degrades due to the up-scaling of parasitics.
U.S. Pat. No. 5,268,330 to Givens et al. describes a process for improving sheet resistance of an integrated circuit device gate.
U.S. Pat. No. 5,554,544 to Hsu describes a field edge method of manufacturing a T-gate LDD pocket device.
U.S. Pat. No. 5,739,066 to Pan describes a semiconductor processing method of forming a conductive gate or gate line over a substrate.
U.S. Pat. No. 6,063,675 to Rodder describes a method of forming a MOSFET using a disposable gate with a sidewall dielectric.
U.S. Pat. No. 5,943,560 to Chang et al. describes a method of fabricating a thin film transistor using ultrahigh vacuum chemical vapor deposition (UHV/CVD) and chemical mechanical polishing (CMP) systems.
U.S. Pat. No. 5,731,239 to Wong et al. describes a method of fabricating self-aligned silicide narrow gate electrodes for field effect transistors (FET) having low sheet resistance.
Accordingly, it is an object of one or more embodiments of the present invention to provide an improved method of fabricating high fMAX deep submicron MOSFETs.
Other objects will appear hereinafter.
It has now been discovered that the above and other objects of the present invention may be accomplished in the following manner. Specifically, a substrate having a MOSFET formed thereon is provided. The MOSFET having a source and a drain and including a silicide portion over a gate electrode. A first ILD layer is formed over the substrate and the MOSFET. The first ILD layer is planarized to expose the silicide portion over the gate electrode. A metal gate portion is formed over the planarized first ILD layer and over the silicide portion over the gate electrode. The metal gate portion having a width substantially greater than the width of the silicide portion over the gate electrode. A second ILD layer is formed over the metal gate portion and the first ILD layer. A first metal contact is formed through the second ILD layer contacting the metal gate portion, and a second metal contact is formed through the second and first ILD layers contacting the drain completing the formation of the high fMAX deep submicron MOSFET. Whereby the width of the metal gate portion reduces Rg and increases the fMAX of the high fMAX deep submicron MOSFET.